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One Dark Pro
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Andromeda
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Ayu Dark
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Ayu Mirage
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Ayu Light
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Cobalt2
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Night Owl
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Night Owl Light
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Noctis
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Noctis Azureus
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Noctis Bordo
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Noctis Hibernus
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Noctis Lilac
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Noctis Lux
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Noctis Minimus
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Noctis Obscuro
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Noctis Sereno
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Noctis Uva
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Noctis Viola
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Palenight
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Pico 8
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Shades of Purple
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Shades of Purple SD
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Synthwave '84
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Tokyo Night
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Tokyo Night Storm
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Tokyo Night Light
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Winter is Coming
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Winter is Coming Light
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog
Winter is Coming Dark
// File : tb_top.sv
module tb_top ();
reg clk;
reg resetn;
reg d;
wire q;
// Instantiate the design
d_ff d_ff0 ( .clk (clk),
.resetn (resetn),
.d (d),
.q (q));
// Create a clock
always #10 clk <= ~clk;
initial begin
resetn <= 0;
d <= 0;
#10 resetn <= 1;
#5 d <= 1;
#8 d <= 0;
#2 d <= 1;
#10 d <= 0;
end
endmodule
// From https://www.chipverify.com/tutorials/systemverilog